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AS4C256K16FO
(R)
5V 256K X 16 CMOS DRAM (Fast Page Mode) Features
* Organization: 262,144 words x 16 bits * High speed - 25/30/35/50 ns RAS access time - 12/16/18/25 ns column address access time - 7/10/10/10 ns CAS access time * Low power consumption - Active: 770 mW max (ASAS4C256K16FO-50) - Standby: 5.5 mW max, CMOS I/O * Fast page mode * AS4C256K16FO-50 timings are also valid for
AS4C256K16FO-60.
* Refresh - 512 refresh cycles, 8 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh - Self-refresh option is available for new generation device only. Contact Alliance for more information. * Read-modify-write * TTL-compatible, three-state I/O * JEDEC standard packages - 400 mil, 40-pin SOJ - 400 mil, 40/44-pin TSOP II * Single 5V power supply/built-in Vbb generator * Latch-up current > 200 mA
Pin arrangement
SOJ VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 GND VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 VCC TSOP II 44 1 43 2 42 3 41 4 40 5 39 6 38 7 37 8 36 9 35 10 ASC256K16FO 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS
Pin designation
Pin(s) A0 to A8 RAS I/O0 to I/O15 OE UCAS LCAS WE VCC GND Description Address inputs Row address strobe Input/output Output enable Column address strobe, upper byte Column address strobe, lower byte Read/write control Power (+5V 10%) Ground
Selection guide
Symbol Maximum RAS access time Maximum column address access time Maximum CAS access time Maximum output enable (OE) access time Minimum read or write cycle time Minimum EDO page mode cycle time Maximum operating current Maximum CMOS standby current
4/11/01; V.0.9.1
ASC256K16FO
-25 25 12 7 7 40 12 200 2.0
-30 30 16 10 10 65 12 180 2.0
-35 35 18 10 10 70 14 160 2.0
-50 50 25 10 10 85 25 140 2.0
Unit ns ns ns ns ns ns mA mA
tRAC tCAA tCAC tOEA tRC tPC ICC1 ICC2
Alliance Semiconductor
P. 1 of 25
Copyright (c) Alliance Semiconductor. All rights reserved.
AS4C256K16FO
(R)
Functional description
The AS4C256K16FO is a high-performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) device organized as 262,144 words x 16 bits. The AS4C256K16FO is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The AS4C256K16FO features a high-speed page mode operation in which high speed read, write and read-write are performed on any of the 512 x 16 bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease the system-level timing constraints associated with multiplexed addressing. Output is tri-stated by a column address strobe (CAS) which acts as an output enable independent of RAS. Very fast CAS to output access time eases system design. Refresh on the 512 address combinations of A0-A8 during an 8 ms period is accomplished by performing any of the following:
* * * * * RAS-only refresh cycles Hidden refresh cycles CAS-before-RAS refresh cycles Normal read or write cycles Self-refresh cycles.*
The AS4C256K16FO is available in standard 40-pin plastic SOJ and 44-pin TSOP II packages compatible with widely available automated testing and insertion equipment. System level features include single power supply of 5V 10% tolerance and direct interface with TTL logic families.
Logic block diagram
VCC GND Refresh controller Column decoder Sense amp Data I/O buffer I/O0 to I/O15
RAS
RAS clock generator CAS clock generator
UCAS LCAS
A0 A1 A2 A3 A4 A5 A6 A7 A8
Addreess buffers
OE Row decoder 512x512x16 array (4,194,304) Substrate bias generator
WE
WE clock generator
Recommended operating conditions
Parameter Supply voltage Input voltage Symbol VCC GND VIH VIL Min 4.5 0.0 2.4 -1.0 Typ 5.0 0.0 - - Max 5.5 0.0 VCC + 1 0.8 Unit V V V V
* Self-refresh option is available for new generation device only. Contact Alliance for more information.
4/11/01; V.0.9.1
Alliance Semiconductor
P. 2 of 25
AS4C256K16FO
(R)
Absolute maximum ratings
Parameter Input voltage Output voltage Power supply voltage Operating temperature Storage temperature (plastic) Soldering temperature x time Power dissipation Short circuit output current Latch-up current Symbol VIN VOUT VCC TOPR TSTG TSOLDER PD IOUT Min -1.0 -1.0 -1.0 0 -55 - - - 200 Max +7.0 +7.0 +7.0 +70 +150 260 x 10 1 50 - Unit V V V C C C x sec W mA mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC electrical characteristics
Parameter Symbol Input leakage IIL current Output leakage IOL current Operating power supply ICC1 current TTL standby power supply ICC2 current Average power supply current, ICC3 RAS refresh mode Fast page mode average power ICC4 supply current CMOS standby power supply ICC5 current CAS-before-RAS refresh power ICC6 supply current VOH Output voltage VOL Self refresh current ICC7 Test conditions 0V VIN + 5.5V pins not under test = 0V DOUT disabled, 0V VOUT + 5.5V RAS, UCAS, LCAS, address cycling; tRC = min RAS = UCAS = LCAS = VIH RAS cycling, UCAS = LCAS = VIH, tRC = min RAS = UCAS = LCAS = VIL, address cycling: tSC = min RAS = UCAS = LCAS = VCC - 0.2V RAS, UCAS, LCAS, cycling; tRC = min
(VCC = 5 10%, GND = 0V, Ta = 0 C to +70 C)
-25 Min Max -10 -10 - 10 10 200 -30 Min Max -10 -10 - 10 10 180 -35 Min Max -10 -10 - 10 10 160 -50 Min Max Unit Note -10 -10 - 10 10 140 A A mA 1,2
-
2.0
-
2.0
-
2.0
-
2.0
mA
-
120
-
200
-
190
-
140
mA
1
-
130
-
190
-
180
-
70
mA
1,2
-
0.60
-
1.0
-
1.0
-
1.0
mA
-
120 - 0.4 2.0
- 2.4 - -
200 - 0.4 2.0
- 2.4 - -
190 - 0.4 2.0
- 2.4 - -
140 - 0.4 2.0
mA V V mA
1
IOUT = - 5.0 mA 2.4 IOUT = 4.2 mA - RAS = UCAS = LCAS = VIL, WE = OE = A0 - A8 = VCC -0.2V, - DQ0 - DQ15 = VCC - 0.2V, 0.2V are open
4/11/01; V.0.9.1
Alliance Semiconductor
P. 3 of 25
AS4C256K16FO
(R)
AC parameters common to all waveforms
Standard Symbol tRC tRP tRAS tCAS tRCD tRAD tRSH(R) tCSH tCRP tASR tRAH tT tREF tCLZ -25 Parameter Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS hold time (read cycle) RAS to CAS hold time CAS to RAS precharge time Row address setup time Row address hold time Transition time (rise and fall) Refresh period CAS to output in low Z Min 45 15 25 4 10 8 7 20 5 0 5 1.5 - 0 Max - - 75K - 17 13 - - - - - 50 8 -
(VCC = 5V 10%, GND = 0V, Ta = 0 C to +70 C)
-30 Min 65 25 30 5 15 10 10 30 5 0 5 1.5 - 0 Max - - 75K - 20 14 - - - - - 50 8 - 70 25 35 6 16 11 10 35 5 0 6 1.5 - 0 -35 Min Max - - 75K - 24 17 - - - - - 50 8 - 85 25 50 10 15 15 10 50 5 0 9 3 - 3 -50 Min Max - - 75K - 35 25 - - - - - 50 8 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ms ns 4,5 3 8 6 7 Notes
Read cycle
Standard Symbol tRAC tCAC tAA tAR(R) tRCS tRCH tRRH tRAL tCPN tOFF -25 Parameter Access time from RAS Access time from CAS Access time from address Column add hold from RAS Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS Lead time CAS precharge time Output buffer turn-off time Min - - - 19 0 0 0 12 4 0 Max 25 7 12 - - - - - - 6
(VCC = 5V10%, GND = 0V, Ta = 0 C to + 70 C)
-30 Min - - - 26 0 0 0 16 3 0 Max 30 10 16 - - - - - - 8 Min - - - 28 0 0 0 18 4 0 -35 Max 35 10 18 - - - - - - 8 - - - 30 0 0 0 25 5 0 -50 Min Max 50 10 25 - - - - - - 8 Unit ns ns ns ns ns ns ns ns ns ns 8,10 9 9 Notes 6 6,13 7,13
4/11/01; V.0.9.1
Alliance Semiconductor
P. 4 of 25
AS4C256K16FO
(R)
Write cycle
Standard Symbol tASC tCAH tAWR tWCS tWCH tWCR tWP tRWL tCWL tDS tDH tDHR -25 Parameter Column address setup time Column address hold time Column address hold time to RAS Write command setup time Write command hold time Write command hold time to RAS Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Data-in hold time to RAS Min 0 5 19 0 5 19 5 7 5 0 5 19 Max - - - - - - - - - - - -
(VCC = 5V 10%, GND = 0V, Ta = 0 C to +70 C)
-30 Min 0 5 26 0 5 26 5 10 10 0 5 26 Max - - - - - - - - - - - - 0 5 28 0 5 28 5 11 11 0 5 28 -35 Min Max - - - - - - - - - - - - 0 9 30 0 9 30 9 12 12 0 9 30 -50 Min Max - - - - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns 12 12 11 11 Notes
Read-modify-write cycle
Standard Symbol tRWC tRWD tCWD tAWD -25 Parameter Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time Min 100 34 17 21 7 15 Max - - - - - -
(VCC = 5V 10%, GND = 0V, Ta = 0 C to +70 C)
-30 Min 100 50 26 32 10 15 Max - - - - - - -35 Min 105 54 28 35 10 15 Max - - - - - - -50 Min 120 60 30 40 12 15 Max - - - - - - Unit ns ns ns ns ns ns 11 11 11 Notes
tRSH(W) CAS to RAS hold time (write) tCAS(W) CAS pulse width (write)
Fast page mode cycle
Standard Symbol tPC tCAP tCP tPCM tCRW tRASP -25 Parameter Read or write cycle time Access time from CAS precharge CAS precharge time Fast page mode RMW cycle Page mode CAS pulse width (RMW) RAS pulse width Min 8 - 3 56 44 25
(VCC = 5V 10%, GND = 0V, Ta = 0 C to +70 C)
-30 Min 12 - 3 56 44 30 Max - 19 - - - 75K - 14 - - - 75K 14 - 4 58 46 35 -35 Min Max - 21 - - - 75K 25 - 5 60 50 50 -50 Min Max - 23 - - - 75K Unit ns ns ns ns ns ns Notes 14 13 Max
4/11/01; V.0.9.1
Alliance Semiconductor
P. 5 of 25
AS4C256K16FO
(R)
Refresh cycle
Standard Symbol Parameter tCSR CAS setup time (CAS-before-RAS) tCHR CAS hold time (CAS-before-RAS) tRPC RAS precharge to CAS hold time CAS precharge time tCPT (CAS-before-RAS counter test)
(VCC = 5V 10%, GND = 0V, Ta = 0 C to +70 C)
-25 Min Max 10 - 7 - 0 - 8 - -30 Min Max 10 - 7 - 0 - 8 - -35 Min Max 10 - 8 - 0 - 8 - -50 Min Max 10 - 10 - 0 - 8 - Unit ns ns ns ns Notes 3 3
Output enable
Standard Symbol tROH tOEA tOED tOEZ tOEH Parameter RAS hold time referenced to OE OE access time OE to data delay Output buffer turnoff delay from OE OE command hold time
(VCC = 5V 10%, GND = 0V, Ta = 0 C to +70 C)
-25 Min Max 5 - - 8 5 - - 6 5 - -30 Min Max 5 - - 10 5 - - 8 8 - -35 Min Max 5 - - 10 5 - - 8 8 - -50 Min Max 5 - - 10 8 - - 8 8 - Unit ns ns ns ns ns Notes
8
Self refresh cycle
(VCC = 5V 10%, GND = 0V, Ta = 0 C to +70 C)
-30 -35 Min Max Min Max 100K - 100K - 85 - 85 - 30 - 30 - -50 Min Max 100K - 85 - 30 - Unit ns ns ns Notes
-25 Standard Symbol Parameter Min Max tRASS RAS pulse width (CBR self refresh) 100K - tRPS RAS precharge time (CBR self refresh) 85 - tCHS CAS hold time (CBR self refresh) 30 -
Notes
1 2 3 ICC1, ICC3, ICC4, and ICC6 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. An initial pause of 200 s is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8 ms). AC characteristics assume tT = 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, VIL (min) GND and VIH (max) VCC. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. Assumes three state test load (5 pF and a 380 Thevenin equivalent). Either tRCH or tRRH must be satisfied for a read cycle. tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS tWS (min) and tWH tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If tRWD tRWD (min), tCWD tCWD (min) and tAWD tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles. Access time is determined by the longest of tCAA or tCAC or tCAP. tASC tCP to achieve tPC (min) and tCAP (max) values. These parameters are sampled, but not 100% tested.
4 5 6 7 8 9 10 11
12 13 14 15
4/11/01; V.0.9.1
Alliance Semiconductor
P. 6 of 25
AS4C256K16FO
(R)
Key to switching waveforms
Rising input Falling input Undefined/don't care
Read cycle waveform
tRC tRAS tRCD RAS tCSH tCRP UCAS, LCAS tAR tRAD tASR Address Row Address tRAH Col Address tRRH tRCH WE tROH OE tRAC tAA tCLZ I/O tOEA tCAC Data Out tOEZ tOFF tRAL tASC tRCS tCAS tCAH tRSH tRP
4/11/01; V.0.9.1
Alliance Semiconductor
P. 7 of 25
AS4C256K16FO
(R)
Upper byte read waveform
tRAS RAS tRCD tCSH tCRP UCAS tCRP LCAS tRAH tRAD tASR Address Row tRCS WE tROH OE tOEA tRAC tCLZ Upper I/O Lower I/O tAA tOEZ tCAC Data Out tOFF tASC Column tRCH tRRH tRAL tCAH tRSH tCAS tCRP tRC tRP
Lower byte read waveform
tRAS RAS tRCD tCSH tCRP LCAS tCRP UCAS tRAH tRAD tASR Address WE tROH OE Upper I/O tOEA tRAC tAA tCLZ Lower I/O tOEZ tCAC Data Out tOFF Row Column tRCS tRCH tRRH tASC tRAL tCAH tCAS tRSH tCRP tRC tRP
4/11/01; V.0.9.1
Alliance Semiconductor
P. 8 of 25
AS4C256K16FO
(R)
Early write waveform
tRC tRAS RAS tCSH tCRP UCAS, LCAS tAWR tRAD tASR Address Row Address tRAH tRAL tASC tCAH Col Address tWCR tCWL tRWL tWP tWCS WE tWCH tRCD tRSH tCAS tRP
OE tDHR tDS I/O tDH Data In
4/11/01; V.0.9.1
Alliance Semiconductor
P. 9 of 25
AS4C256K16FO
(R)
Upper byte early write waveform
tRAS RAS tASR Address tRAH Row Address tASC tRCD tCSH tCRP UCAS tCRP LCAS tWCS tWCR tWP WE OE tDHR Upper I/O Lower I/O tDS Data In tDH tCWL tWCH tRWL tRPC tCAS tCRP tRAD tAWR tRAL Column Address tCAH tRSH tRC tRP
4/11/01; V.0.9.1
Alliance Semiconductor
P. 10 of 25
AS4C256K16FO
(R)
Lower byte early write waveform
tRAS RAS tRAD tASR Address UCAS tASC tRCD tCSH tCRP LCAS tWCR tWCS WE OE Upper I/O tDHR Lower I/O tDS Data In tDH tRSH tRWL tCWL tWP tCAH tCAS tCRP Row Address tCRP tAWR tRAH Column Address tRPC tRAL tRC tRP
tWCH
Write waveform
tRAS RAS tCSH tCRP UCAS, LCAS tAWR tASR Address Row Address tRAD tRAH tASC tCAH Col Address tWCR tRWL tCWL tRCD tRSH tCAS tRAL tRC tRP
tWP tOEH
WE OE tDHR tOED I/O tDH Data In tDS
4/11/01; V.0.9.1
Alliance Semiconductor
P. 11 of 25
AS4C256K16FO
(R)
Upper byte write waveform
tRC tRAS RAS tRAD tAWR tASR Address Row Address tRCD tCRP UCAS tCRP LCAS tCWL tRWL tWP WE tOEH OE tDS Upper I/O Lower I/O Data In tOED tDH tRPC tASC tRAH Column Address tCSH tRSH tCAH tCAS tCRP tRAL tRP
4/11/01; V.0.9.1
Alliance Semiconductor
P. 12 of 25
AS4C256K16FO
(R)
Lower byte write waveform
tRC tRAS RAS tRAD tASR tRAH Address Row Address tRCD tCSH tCRP LCAS tCRP UCAS tCWL tRWL tWP WE tOEH OE Upper I/O tDS Lower I/O Data In tDH tRPC tACS tRSH tCRP tAWR tRAL Column Address tCAH tCAS tRP
Read-modify-write waveform
tRAS RAS tCRP UCAS, LCAS tRAD tASR Address Row Address tRAH Col Address tRWD tAWD tRCS WE OE tRAC tAA tCAC tCLZ Data Out tDS tDH Data In tOEA tOEZ tCWD tOED tRCD tCSH tAR tRAL tASC tCAH tRWL tCWL tWP tRWC tCAS tRSH tRP
I/O
4/11/01; V.0.9.1
Alliance Semiconductor
P. 13 of 25
AS4C256K16FO
(R)
Upper byte read-modify-write waveform
tRAS RAS tCSH tRCD UCAS tCRP tCRP LCAS tASR Address tRAD tRAH Row Column Address tRWD tAWD tRCS WE OE Upper Input tCLZ tCAC tAA tRAC Upper Output Data Out Lower Input Lower Output Data Out tOED tOED Data In tOEZ tDS tCWD tOEA tACS tRAL tCAH tCWL tRWL tWP tCAS tRSH tCRP tRWC tRP
tRPC
4/11/01; V.0.9.1
Alliance Semiconductor
P. 14 of 25
AS4C256K16FO
(R)
Lower byte read-modify write waveform
tRWC tRAS RAS tCRP UCAS tCSH tRCD tCRP LCAS tRAD tASR Address Row tRCS WE tOEA OE Upper Input Upper Output Data Out tOED Lower Input tRAC tAA tCAC tCLZ Data In tOEZ Data Out tDS tACS tRAH Column Address tRWD tAWD tCWD tCWL tRWL tWP tRAL tCAH tCAS tRSH tCRP tRPC tRP
Lower Output
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Alliance Semiconductor
P. 15 of 25
AS4C256K16FO
(R)
Fast page mode read waveform
tRASP RAS tCSH tCRP UCAS, LCAS tAR tRAD tASR Address WE tOEA OE tRAC tCLZ tCAC tAA Data Out tOEZ tOFF Data Out tCAP Data Out tOEA Row tRAH Col Address tRCS tRCH tASC Col Address tRCS tCAH Col Address tRCH tRRH tRAL tRCD tCAS tCP tRSH tPC tRP
I/O
Fast page mode byte read waveform
tRASP RAS tCSH UCAS tCRP tRCD tCP tPC tCRP LCAS tASR Address Row tRCS WE tOEA OE tAA tCAP Upper I/O tRAC Lower I/O Data Out 1 Data Out n tAA tOFF tOEZ tCAC tCLZ Data Out 2 tAA tCAP tCAC tCLZ tOFF tOEZ tOEA tOEA tRAH tRAD tCAH tCAH Column 2 tASC tASC Column 1 tRCH tCAS tCAS tPC tCP tRAL tASC Column n tRCS tRCH tCAH tRPC tRSH tCAS tCAS tCRP tRP
tRCS
tCAC tCLZ
tOFF tOEZ
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Alliance Semiconductor
P. 16 of 25
AS4C256K16FO
(R)
Fast page mode early write waveform
tRASP tRAH RAS tCRP tRCD tCSH tCAS UCAS, LCAS tASR Address tRAD Row address tAR Col address Col Address tASC tWCS tPC tCP tRAL Col Address tCWL tWP tOEH tCAH tRSH tRWL
tWCH WE OE tHDR tDS I/O tDH Data In Data In tOED
Data In
Fast page mode byte early write waveform
RAS tCRP UCAS tCRP LCAS tRAD tRAH tASR Address Row tASC Column 1 tWCH tWP tCAH tASC Column 2 tWCH tCAH tRAL tASC Column n tCAH tPC tCP tPC tCP tCAS tRPC tCSH tRCD tCAS tRASP tRSH tCAS tRP tCRP
tRWL tWCS tCWL WE OE tDS Upper I/O tDS Lower I/O Data In 1 Data In n tDH Data In 2 tDS tDH tDH tWCS tWP tCWL tWCS tWP tWCH tCWL
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Alliance Semiconductor
P. 17 of 25
AS4C256K16FO
(R)
Fast page mode read-modify-write waveform
tRASP RAS tCSH tRCD UCAS, LCAS Address tRAD tASR Row Ad tRCS WE tOEA OE tAA tRAC tCLZ tCAC I/O Data In Data Out tDS tDH tDS tCLZ tCAC Data In Data Out tCAP tCLZ tCAC Data In Data Out tOEZ tOED tOEA tRAH Col Ad tRWD tCWD tAWD tCAH Col Ad tCWL tCWD tCAH tPCM tCAS tCP tRAL tCAH Col Address tCWD tAWD tRWL tCWL tWP tCRP tRP
CAS-before-RAS refresh waveform
tRC tRP RAS tRPC tCPN tCSR UCAS, LCAS tOFF I/O tCHR tRAS
(WE = VIH)
RAS-only refresh waveform
tRC tRAS RAS tCRP UCAS, LCAS Address tARS Row Address tRAH tRPC tRP
(WE = OE = VIH or VIL)
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P. 18 of 25
AS4C256K16FO
(R)
Fast page mode byte read-modify-write waveform
tRASP RAS tCSH tRCD tRSH tCAS tPCM tCAS tRP
tCRP UCAS
tCAS
tCRP
tCP LCAS tRAD tRAH tASR Address tRCS R tAWD tASC C1 tCWD tWP tOEA OE tOED tDS Upper Input tRAC Data In 1 tAA tCAC Data Out 1 Lower Input tCAP tAA Lower Output tCAC tOEZ tCLZ tDH tCAH C2
tCP
tCAH tAWD tASC
tRAL tASC Cn tCWD tWP
tCAH tAWD
tRWD WE
tCWL
tCWL
tRWL tCWD tCWL tWP tOEA
tOEA tOED tDS tCAP tCAC tAA
tDH
Data In n tOEZ tCLZ tDH tDS Data In 2 tOEZ Data Out n
Upper Output tOED
tCLZ Data Out 2
4/11/01; V.0.9.1
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P. 19 of 25
AS4C256K16FO
(R)
Hidden refresh waveform (read)
tRC tRAS RAS tCRP tRCD CAS tRAD tRAH tASR Address Row tRCS WE tOEA OE tRAC tAA tCAC tCLZ I/O Data Out tOFF tOEZ tAR tASC Col Address tRRH tCHR tRSH tCRP tPR tRAS tRC tPR
Hidden refresh waveform (write)
tRC tRAS RAS tCRP UCAS, LCAS tRAD tASR Address tRAH tASC tRAL tCAH Col Address tRWL tWCR tWCS WE tDS I/O OE tDHR Data In tDH tWP tWCH tRCD tAR tRSH tRP
Row Address
4/11/01; V.0.9.1
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P. 20 of 25
AS4C256K16FO
(R)
CAS before RAS refresh counter test waveform
tRAS RAS tCSR UCAS, LCAS tRAL tCAH Address Col Address tAA tCAC tCLZ I/O Read Cycle tRCS WE tOEA OE tRWL tCWL tROH Data Out tRRH tRCH tOFF tCHR tCPT tCAS tRSH tRP
tWCS Write Cycle WE
tWP tWCH
I/O OE
tDH tDS Data In
tRCS tAWD WE Read-Write Cycle tOEA OE tAA tCLZ tCAC I/O Data Out tOEZ tDS Data In tDH tOED tCWD tCWL
tWP
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P. 21 of 25
AS4C256K16FO
(R)
CAS-before-RAS self refresh cycle
tRP RAS tRPC tCP tCSR UCAS, LCAS DQ tCHS tRPC tRASS tRPS
tCEZ
Typical AC and DC characteristics
1.5 1.4 Normalized access time 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 Supply voltage (V) Typical supply current ICC vs. supply voltage VCC 6.0 Ta = 25C Normalized access time Normalized access time tRAC vs. supply voltage VCC 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 -55 -10 35 80 Ambient temperature (C) Typical supply current ICC vs. ambient temperature Ta 125 Typical access time Normalized access time tRAC vs. ambient temperature Ta 100 90 80 -70 70 60 50 40 30 50 100 150 200 Load capacitance (pF) Typical power-on current IPO vs. cycle rate 1/tRC 250 -60 -50 Typical access time tRAC vs. load capacitance CL
70 60 Supply current (mA) 50 40 30 20 10 0.0 4.0
70 60 50 40 30 20 10
35 30 Power-on current (mA) 25 20 15 10 5 0.0 2
Supply current (mA) 4.5 5.0 5.5 Supply voltage (V)
6.0
0.0 -55
-10 35 80 125 Ambient temperature (C)
4 6 8 Cycle rate (MHz)
10
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Alliance Semiconductor
P. 22 of 25
AS4C256K16FO
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35 30 Refresh current (mA)
Typical refresh current ICC3 vs. supply voltage VCC
35 30 25 20 15 10 5 Refresh current (mA)
Typical refresh current ICC3 vs. Ambient temperature Ta
3.5 3.0 Stand-by current (mA) 2.5 2.0 1.5 1.0 0.5 0
Typical TTL stand-by current ICC2 vs. supply voltage VCC
25 20 15 10 5 0 4.0 4.5 5.0 5.5 Supply voltage (V) 6.0
0 0.0
20 40 60 80 Ambient temperature (C) Typical output sink current IOL vs. output voltage VOL Output source current (mA)
4.0
4.5 5.0 5.5 Supply voltage (V)
6.0
3.5 3.0 Stand-by current (mA) 2.5 2.0 1.5 1.0 0.5 0.0
Typical TTL stand-by current ICC2 vs. ambient temperature Ta Output sink current (mA)
70 60 50 40 30 20 10 0.0 0.0
70 60 50 40 30 20 10 0.0
Typical output source current IOH vs. output voltage VOH
0
20 40 60 80 Ambient temperature (C)
0.5 1.0 1.5 Output voltage (V)
2.0
0.0
1.0 2.0 3.0 Output voltage (V)
4.0
35 Fast page mode current (mA) 30 25 20 15 10 5 0.0
Typical fast page mode current ICC4 vs. ambient temperature Ta Fast page mode current (mA) 0 20 40 60 Ambient temperature (C)
35 30 25 20 15 10 5
Typical fast page mode current ICC4 vs. supply voltage VCC
80
0.0 4.0
4.5 5.0 5.5 Supply voltage (V)
6.0
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Alliance Semiconductor
P. 23 of 25
AS4C256K16FO
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Package dimensions
44434241403938373635343332313029282726252423 c
40/44-pin TSOP II
E He
1 2 3 4 5 6 7 8 910111213141516171819202122 D l 0-5 A1 b e D
A
A2
A A1 A2 b c D E He e l
44-pin TSOP II Min Max (mm) (mm) 1.2 0.05 0.95 1.05 0.30 0.45 0.127 (typical) 18.28 18.54 10.03 10.29 11.56 11.96 0.80 (typical) 0.40 0.60 40-pin SOJ 400 mil Min Max 0.128 0.148 0.026 1.105 1.115 0.026 0.032 0.020 0.007 0.013 1.020 1.035 0.370 (typical) 0.395 0.405 0.435 0.445
0.050 (typical)
e 40-pin SOJ
E1 E2
Pin 1
B A b Seating Plane A2 E2
c
A1
A A1 A2 B b c D E E1 E2
e
Capacitance
Parameter Input capacitance I/O capacitance Symbol CIN1 CIN2 CI/O
(f = 1 MHz, Ta = Room Temperature, VCC = 5V 10%)
Signals A0 to A8 RAS, UCAS, LCAS, WE, OE I/O0 to I/O15 Test conditions VIN = 0V VIN = 0V VIN = VOUT = 0V Max 5 7 7 Unit pF pF pF
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Alliance Semiconductor
P. 24 of 25
AS4C256K16FO
(R)
Ordering codes
-25 ns AS4C256K16F0-25JC AS4C256K16F0-25JI AS4C256K16F0-25TC AS4C256K16F0-25TI -30 ns AS4C256K16F0-30JC AS4C256K16F0-30JI AS4C256K16F0-30TC AS4C256K16F0-30TI -35 ns AS4C256K16F0-35JC AS4C256K16F0-35JI AS4C256K16F0-35TC AS4C256K16F0-35TI -50 ns AS4C256K16FO-50JC AS4C256K16FO-50JI AS4C256K16FO-50TC AS4C256K16FO-50TI
Part numbering system
AS4C DRAM prefix 256K16F0 Device number -XX RAS access time X Package: J = Plastic SOJ, 400 mil, 40-pin T = TSOP II, 400 mil, 40/44-pin C/I Temperature Range: C= Commercial (0 C to 70 C) I= Industrial (-40C to 85C)
4/11/01; V.0.9.1
Alliance Semiconductor
P. 25 of 25

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